xine-lib  1.2.10
mmx.h
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1 /* mmx.h
2 
3  MultiMedia eXtensions GCC interface library for IA32.
4 
5  To use this library, simply include this header file
6  and compile with GCC. You MUST have inlining enabled
7  in order for mmx_ok() to work; this can be done by
8  simply using -O on the GCC command line.
9 
10  Compiling with -DMMX_TRACE will cause detailed trace
11  output to be sent to stderr for each mmx operation.
12  This adds lots of code, and obviously slows execution to
13  a crawl, but can be very useful for debugging.
14 
15  THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
16  EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
17  LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
18  AND FITNESS FOR ANY PARTICULAR PURPOSE.
19 
20  1997-99 by H. Dietz and R. Fisher
21 
22  Notes:
23  It appears that the latest gas has the pand problem fixed, therefore
24  I'll undefine BROKEN_PAND by default.
25 */
26 
27 #ifndef _MMX_H
28 #define _MMX_H
29 
30 #ifdef HAVE_CONFIG_H
31 # include "config.h"
32 #endif
33 
34 #include <xine/attributes.h>
35 
36 #include "goom_graphic.h"
37 
38 /* Warning: at this writing, the version of GAS packaged
39  with most Linux distributions does not handle the
40  parallel AND operation mnemonic correctly. If the
41  symbol BROKEN_PAND is defined, a slower alternative
42  coding will be used. If execution of mmxtest results
43  in an illegal instruction fault, define this symbol.
44 */
45 #undef BROKEN_PAND
46 
47 
48 /* The type of an value that fits in an MMX register
49  (note that long long constant values MUST be suffixed
50  by LL and unsigned long long values by ULL, lest
51  they be truncated by the compiler)
52 */
53 typedef union {
54  long long q; /* Quadword (64-bit) value */
55  unsigned long long uq; /* Unsigned Quadword */
56  int d[2]; /* 2 Doubleword (32-bit) values */
57  unsigned int ud[2]; /* 2 Unsigned Doubleword */
58  short w[4]; /* 4 Word (16-bit) values */
59  unsigned short uw[4]; /* 4 Unsigned Word */
60  char b[8]; /* 8 Byte (8-bit) values */
61  unsigned char ub[8]; /* 8 Unsigned Byte */
62  float s[2]; /* Single-precision (32-bit) value */
63 } ATTR_ALIGN(8) mmx_t; /* On an 8-byte (64-bit) boundary */
64 
65 
66 
67 /* Function to test if multimedia instructions are supported...
68 */
69 static int
71 {
72  /* Returns 1 if MMX instructions are supported,
73  3 if Cyrix MMX and Extended MMX instructions are supported
74  5 if AMD MMX and 3DNow! instructions are supported
75  13 if AMD Extended MMX, &3dNow supported
76  0 if hardware does not support any of these
77  */
78 #if defined(ARCH_X86_X32) || defined(ARCH_X86_64)
79  return 13;
80 #else
81  register int rval = 0;
82 
83  __asm__ __volatile__ (
84  /* See if CPUID instruction is supported ... */
85  /* ... Get copies of EFLAGS into eax and ecx */
86  "pushl %%ebx\n\t"
87  "pushf\n\t"
88  "popl %%eax\n\t"
89  "movl %%eax, %%ecx\n\t"
90 
91  /* ... Toggle the ID bit in one copy and store */
92  /* to the EFLAGS reg */
93  "xorl $0x200000, %%eax\n\t"
94  "push %%eax\n\t"
95  "popf\n\t"
96 
97  /* ... Get the (hopefully modified) EFLAGS */
98  "pushf\n\t"
99  "popl %%eax\n\t"
100 
101  /* ... Compare and test result */
102  "xorl %%eax, %%ecx\n\t"
103  "testl $0x200000, %%ecx\n\t"
104  "jz NotSupported1\n\t" /* CPUID not supported */
105 
106 
107  /* Get standard CPUID information, and
108  go to a specific vendor section */
109  "movl $0, %%eax\n\t"
110  "cpuid\n\t"
111 
112  /* Check for Intel */
113  "cmpl $0x756e6547, %%ebx\n\t"
114  "jne TryAMD\n\t"
115  "cmpl $0x49656e69, %%edx\n\t"
116  "jne TryAMD\n\t"
117  "cmpl $0x6c65746e, %%ecx\n"
118  "jne TryAMD\n\t"
119  "jmp Intel\n\t"
120 
121  /* Check for AMD */
122  "\nTryAMD:\n\t"
123  "cmpl $0x68747541, %%ebx\n\t"
124  "jne TryCyrix\n\t"
125  "cmpl $0x69746e65, %%edx\n\t"
126  "jne TryCyrix\n\t"
127  "cmpl $0x444d4163, %%ecx\n"
128  "jne TryCyrix\n\t"
129  "jmp AMD\n\t"
130 
131  /* Check for Cyrix */
132  "\nTryCyrix:\n\t"
133  "cmpl $0x69727943, %%ebx\n\t"
134  "jne NotSupported2\n\t"
135  "cmpl $0x736e4978, %%edx\n\t"
136  "jne NotSupported3\n\t"
137  "cmpl $0x64616574, %%ecx\n\t"
138  "jne NotSupported4\n\t"
139  /* Drop through to Cyrix... */
140 
141 
142  /* Cyrix Section */
143  /* See if extended CPUID level 80000001 is supported */
144  /* The value of CPUID/80000001 for the 6x86MX is undefined
145  according to the Cyrix CPU Detection Guide (Preliminary
146  Rev. 1.01 table 1), so we'll check the value of eax for
147  CPUID/0 to see if standard CPUID level 2 is supported.
148  According to the table, the only CPU which supports level
149  2 is also the only one which supports extended CPUID levels.
150  */
151  "cmpl $0x2, %%eax\n\t"
152  "jne MMXtest\n\t" /* Use standard CPUID instead */
153 
154  /* Extended CPUID supported (in theory), so get extended
155  features */
156  "movl $0x80000001, %%eax\n\t"
157  "cpuid\n\t"
158  "testl $0x00800000, %%eax\n\t" /* Test for MMX */
159  "jz NotSupported5\n\t" /* MMX not supported */
160  "testl $0x01000000, %%eax\n\t" /* Test for Ext'd MMX */
161  "jnz EMMXSupported\n\t"
162  "movl $1, %0\n\n\t" /* MMX Supported */
163  "jmp Return\n\n"
164  "EMMXSupported:\n\t"
165  "movl $3, %0\n\n\t" /* EMMX and MMX Supported */
166  "jmp Return\n\t"
167 
168 
169  /* AMD Section */
170  "AMD:\n\t"
171 
172  /* See if extended CPUID is supported */
173  "movl $0x80000000, %%eax\n\t"
174  "cpuid\n\t"
175  "cmpl $0x80000000, %%eax\n\t"
176  "jl MMXtest\n\t" /* Use standard CPUID instead */
177 
178  /* Extended CPUID supported, so get extended features */
179  "movl $0x80000001, %%eax\n\t"
180  "cpuid\n\t"
181  "testl $0x00800000, %%edx\n\t" /* Test for MMX */
182  "jz NotSupported6\n\t" /* MMX not supported */
183  "testl $0x80000000, %%edx\n\t" /* Test for 3DNow! */
184  "jnz ThreeDNowSupported\n\t"
185  "movl $1, %0\n\n\t" /* MMX Supported */
186  "jmp Return\n\n"
187  "ThreeDNowSupported:\n\t"
188  "testl $0x40000000, %%edx\n\t" /* Test AMD Extended MMX */
189  "jnz AMDXMMXSupported\n\t"
190  "movl $5, %0\n\n\t" /* 3DNow! and MMX Supported */
191  "jmp Return\n\t"
192  "AMDXMMXSupported:\n\t"
193  "movl $13, %0\n\n\t" /* XMMX, 3DNow! and MMX Supported */
194  "jmp Return\n\t"
195 
196 
197  /* Intel Section */
198  "Intel:\n\t"
199 
200  /* Check for MMX */
201  "MMXtest:\n\t"
202  "movl $1, %%eax\n\t"
203  "cpuid\n\t"
204  "testl $0x00800000, %%edx\n\t" /* Test for MMX */
205  "jz NotSupported7\n\t" /* MMX Not supported */
206  "movl $1, %0\n\n\t" /* MMX Supported */
207  "jmp Return\n\t"
208 
209  /* Nothing supported */
210  "\nNotSupported1:\n\t"
211  "#movl $101, %0\n\n\t"
212  "\nNotSupported2:\n\t"
213  "#movl $102, %0\n\n\t"
214  "\nNotSupported3:\n\t"
215  "#movl $103, %0\n\n\t"
216  "\nNotSupported4:\n\t"
217  "#movl $104, %0\n\n\t"
218  "\nNotSupported5:\n\t"
219  "#movl $105, %0\n\n\t"
220  "\nNotSupported6:\n\t"
221  "#movl $106, %0\n\n\t"
222  "\nNotSupported7:\n\t"
223  "#movl $107, %0\n\n\t"
224  "movl $0, %0\n\n\t"
225 
226  "Return:\n\t"
227  "popl %%ebx\n\t"
228  : "=X" (rval)
229  : /* no input */
230  : "eax", "ecx", "edx"
231  );
232 
233  /* Return */
234  return(rval);
235 #endif
236 }
237 
238 /* Function to test if mmx instructions are supported...
239 */
240 static inline int
241 mmx_ok(void)
242 {
243  /* Returns 1 if MMX instructions are supported, 0 otherwise */
244  return ( mm_support() & 0x1 );
245 }
246 
247 int mmx_supported (void);
248 int xmmx_supported (void);
249 
250 
251 /* MMX optimized implementations */
252 void draw_line_mmx (Pixel *data, int x1, int y1, int x2, int y2, int col, int screenx, int screeny);
253 void draw_line_xmmx (Pixel *data, int x1, int y1, int x2, int y2, int col, int screenx, int screeny);
254 void zoom_filter_mmx (int prevX, int prevY, Pixel *expix1, Pixel *expix2,
255  int *brutS, int *brutD, int buffratio, int precalCoef[16][16]);
256 void zoom_filter_xmmx (int prevX, int prevY, Pixel *expix1, Pixel *expix2,
257  int *lbruS, int *lbruD, int buffratio, int precalCoef[16][16]);
258 
259 
260 /* Helper functions for the instruction macros that follow...
261  (note that memory-to-register, m2r, instructions are nearly
262  as efficient as register-to-register, r2r, instructions;
263  however, memory-to-memory instructions are really simulated
264  as a convenience, and are only 1/3 as efficient)
265 */
266 #ifdef MMX_TRACE
267 
268 /* Include the stuff for printing a trace to stderr...
269 */
270 
271 #include <stdio.h>
272 
273 #define mmx_i2r(op, imm, reg) \
274  { \
275  mmx_t mmx_trace; \
276  mmx_trace.uq = (imm); \
277  printf(#op "_i2r(" #imm "=0x%08x%08x, ", \
278  mmx_trace.d[1], mmx_trace.d[0]); \
279  __asm__ __volatile__ ("movq %%" #reg ", %0" \
280  : "=X" (mmx_trace) \
281  : /* nothing */ ); \
282  printf(#reg "=0x%08x%08x) => ", \
283  mmx_trace.d[1], mmx_trace.d[0]); \
284  __asm__ __volatile__ (#op " %0, %%" #reg \
285  : /* nothing */ \
286  : "X" (imm)); \
287  __asm__ __volatile__ ("movq %%" #reg ", %0" \
288  : "=X" (mmx_trace) \
289  : /* nothing */ ); \
290  printf(#reg "=0x%08x%08x\n", \
291  mmx_trace.d[1], mmx_trace.d[0]); \
292  }
293 
294 #define mmx_m2r(op, mem, reg) \
295  { \
296  mmx_t mmx_trace; \
297  mmx_trace = (mem); \
298  printf(#op "_m2r(" #mem "=0x%08x%08x, ", \
299  mmx_trace.d[1], mmx_trace.d[0]); \
300  __asm__ __volatile__ ("movq %%" #reg ", %0" \
301  : "=X" (mmx_trace) \
302  : /* nothing */ ); \
303  printf(#reg "=0x%08x%08x) => ", \
304  mmx_trace.d[1], mmx_trace.d[0]); \
305  __asm__ __volatile__ (#op " %0, %%" #reg \
306  : /* nothing */ \
307  : "m" (mem)); \
308  __asm__ __volatile__ ("movq %%" #reg ", %0" \
309  : "=X" (mmx_trace) \
310  : /* nothing */ ); \
311  printf(#reg "=0x%08x%08x\n", \
312  mmx_trace.d[1], mmx_trace.d[0]); \
313  }
314 
315 #define mmx_r2m(op, reg, mem) \
316  { \
317  mmx_t mmx_trace; \
318  __asm__ __volatile__ ("movq %%" #reg ", %0" \
319  : "=X" (mmx_trace) \
320  : /* nothing */ ); \
321  printf(#op "_r2m(" #reg "=0x%08x%08x, ", \
322  mmx_trace.d[1], mmx_trace.d[0]); \
323  mmx_trace = (mem); \
324  printf(#mem "=0x%08x%08x) => ", \
325  mmx_trace.d[1], mmx_trace.d[0]); \
326  __asm__ __volatile__ (#op " %%" #reg ", %0" \
327  : "=m" (mem) \
328  : /* nothing */ ); \
329  mmx_trace = (mem); \
330  printf(#mem "=0x%08x%08x\n", \
331  mmx_trace.d[1], mmx_trace.d[0]); \
332  }
333 
334 #define mmx_r2r(op, regs, regd) \
335  { \
336  mmx_t mmx_trace; \
337  __asm__ __volatile__ ("movq %%" #regs ", %0" \
338  : "=X" (mmx_trace) \
339  : /* nothing */ ); \
340  printf(#op "_r2r(" #regs "=0x%08x%08x, ", \
341  mmx_trace.d[1], mmx_trace.d[0]); \
342  __asm__ __volatile__ ("movq %%" #regd ", %0" \
343  : "=X" (mmx_trace) \
344  : /* nothing */ ); \
345  printf(#regd "=0x%08x%08x) => ", \
346  mmx_trace.d[1], mmx_trace.d[0]); \
347  __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
348  __asm__ __volatile__ ("movq %%" #regd ", %0" \
349  : "=X" (mmx_trace) \
350  : /* nothing */ ); \
351  printf(#regd "=0x%08x%08x\n", \
352  mmx_trace.d[1], mmx_trace.d[0]); \
353  }
354 
355 #define mmx_m2m(op, mems, memd) \
356  { \
357  mmx_t mmx_trace; \
358  mmx_trace = (mems); \
359  printf(#op "_m2m(" #mems "=0x%08x%08x, ", \
360  mmx_trace.d[1], mmx_trace.d[0]); \
361  mmx_trace = (memd); \
362  printf(#memd "=0x%08x%08x) => ", \
363  mmx_trace.d[1], mmx_trace.d[0]); \
364  __asm__ __volatile__ ("movq %0, %%mm0\n\t" \
365  #op " %1, %%mm0\n\t" \
366  "movq %%mm0, %0" \
367  : "=m" (memd) \
368  : "m" (mems)); \
369  mmx_trace = (memd); \
370  printf(#memd "=0x%08x%08x\n", \
371  mmx_trace.d[1], mmx_trace.d[0]); \
372  }
373 
374 #else
375 
376 /* These macros are a lot simpler without the tracing...
377 */
378 
379 #define mmx_i2r(op, imm, reg) \
380  __asm__ __volatile__ (#op " %0, %%" #reg \
381  : /* nothing */ \
382  : "X" (imm) )
383 
384 #define mmx_m2r(op, mem, reg) \
385  __asm__ __volatile__ (#op " %0, %%" #reg \
386  : /* nothing */ \
387  : "m" (mem))
388 
389 #define mmx_r2m(op, reg, mem) \
390  __asm__ __volatile__ (#op " %%" #reg ", %0" \
391  : "=m" (mem) \
392  : /* nothing */ )
393 
394 #define mmx_r2r(op, regs, regd) \
395  __asm__ __volatile__ (#op " %" #regs ", %" #regd)
396 
397 #define mmx_m2m(op, mems, memd) \
398  __asm__ __volatile__ ("movq %0, %%mm0\n\t" \
399  #op " %1, %%mm0\n\t" \
400  "movq %%mm0, %0" \
401  : "=m" (memd) \
402  : "m" (mems))
403 
404 #endif
405 
406 
407 /* 1x64 MOVe Quadword
408  (this is both a load and a store...
409  in fact, it is the only way to store)
410 */
411 #define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
412 #define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
413 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
414 #define movq(vars, vard) \
415  __asm__ __volatile__ ("movq %1, %%mm0\n\t" \
416  "movq %%mm0, %0" \
417  : "=X" (vard) \
418  : "X" (vars))
419 
420 
421 /* 1x32 MOVe Doubleword
422  (like movq, this is both load and store...
423  but is most useful for moving things between
424  mmx registers and ordinary registers)
425 */
426 #define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
427 #define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
428 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
429 #define movd(vars, vard) \
430  __asm__ __volatile__ ("movd %1, %%mm0\n\t" \
431  "movd %%mm0, %0" \
432  : "=X" (vard) \
433  : "X" (vars))
434 
435 
436 /* 2x32, 4x16, and 8x8 Parallel ADDs
437 */
438 #define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
439 #define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
440 #define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
441 
442 #define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
443 #define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
444 #define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
445 
446 #define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
447 #define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
448 #define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
449 
450 
451 /* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
452 */
453 #define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
454 #define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
455 #define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
456 
457 #define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
458 #define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
459 #define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
460 
461 
462 /* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
463 */
464 #define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
465 #define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
466 #define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
467 
468 #define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
469 #define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
470 #define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
471 
472 
473 /* 2x32, 4x16, and 8x8 Parallel SUBs
474 */
475 #define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
476 #define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
477 #define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
478 
479 #define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
480 #define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
481 #define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
482 
483 #define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
484 #define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
485 #define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
486 
487 
488 /* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
489 */
490 #define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
491 #define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
492 #define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
493 
494 #define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
495 #define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
496 #define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
497 
498 
499 /* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
500 */
501 #define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
502 #define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
503 #define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
504 
505 #define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
506 #define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
507 #define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
508 
509 
510 /* 4x16 Parallel MULs giving Low 4x16 portions of results
511 */
512 #define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
513 #define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
514 #define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
515 
516 
517 /* 4x16 Parallel MULs giving High 4x16 portions of results
518 */
519 #define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
520 #define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
521 #define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
522 
523 
524 /* 4x16->2x32 Parallel Mul-ADD
525  (muls like pmullw, then adds adjacent 16-bit fields
526  in the multiply result to make the final 2x32 result)
527 */
528 #define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
529 #define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
530 #define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
531 
532 
533 /* 1x64 bitwise AND
534 */
535 #ifdef BROKEN_PAND
536 #define pand_m2r(var, reg) \
537  { \
538  mmx_m2r(pandn, (mmx_t) -1LL, reg); \
539  mmx_m2r(pandn, var, reg); \
540  }
541 #define pand_r2r(regs, regd) \
542  { \
543  mmx_m2r(pandn, (mmx_t) -1LL, regd); \
544  mmx_r2r(pandn, regs, regd) \
545  }
546 #define pand(vars, vard) \
547  { \
548  movq_m2r(vard, mm0); \
549  mmx_m2r(pandn, (mmx_t) -1LL, mm0); \
550  mmx_m2r(pandn, vars, mm0); \
551  movq_r2m(mm0, vard); \
552  }
553 #else
554 #define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
555 #define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
556 #define pand(vars, vard) mmx_m2m(pand, vars, vard)
557 #endif
558 
559 
560 /* 1x64 bitwise AND with Not the destination
561 */
562 #define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
563 #define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
564 #define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
565 
566 
567 /* 1x64 bitwise OR
568 */
569 #define por_m2r(var, reg) mmx_m2r(por, var, reg)
570 #define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
571 #define por(vars, vard) mmx_m2m(por, vars, vard)
572 
573 
574 /* 1x64 bitwise eXclusive OR
575 */
576 #define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
577 #define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
578 #define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
579 
580 
581 /* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
582  (resulting fields are either 0 or -1)
583 */
584 #define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
585 #define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
586 #define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
587 
588 #define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
589 #define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
590 #define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
591 
592 #define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
593 #define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
594 #define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
595 
596 
597 /* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
598  (resulting fields are either 0 or -1)
599 */
600 #define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
601 #define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
602 #define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
603 
604 #define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
605 #define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
606 #define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
607 
608 #define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
609 #define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
610 #define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
611 
612 
613 /* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
614 */
615 #define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
616 #define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
617 #define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
618 #define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
619 
620 #define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg)
621 #define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
622 #define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
623 #define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
624 
625 #define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg)
626 #define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
627 #define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
628 #define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
629 
630 
631 /* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
632 */
633 #define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg)
634 #define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
635 #define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
636 #define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
637 
638 #define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg)
639 #define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
640 #define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
641 #define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
642 
643 #define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg)
644 #define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
645 #define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
646 #define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
647 
648 
649 /* 2x32 and 4x16 Parallel Shift Right Arithmetic
650 */
651 #define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg)
652 #define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
653 #define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
654 #define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
655 
656 #define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg)
657 #define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
658 #define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
659 #define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
660 
661 
662 /* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
663  (packs source and dest fields into dest in that order)
664 */
665 #define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
666 #define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
667 #define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
668 
669 #define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
670 #define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
671 #define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
672 
673 
674 /* 4x16->8x8 PACK and Unsigned Saturate
675  (packs source and dest fields into dest in that order)
676 */
677 #define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
678 #define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
679 #define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
680 
681 
682 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
683  (interleaves low half of dest with low half of source
684  as padding in each result field)
685 */
686 #define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
687 #define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
688 #define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
689 
690 #define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
691 #define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
692 #define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
693 
694 #define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
695 #define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
696 #define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
697 
698 
699 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
700  (interleaves high half of dest with high half of source
701  as padding in each result field)
702 */
703 #define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
704 #define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
705 #define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
706 
707 #define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
708 #define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
709 #define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
710 
711 #define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
712 #define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
713 #define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
714 
715 
716 /* Empty MMx State
717  (used to clean-up when going from mmx to float use
718  of the registers that are shared by both; note that
719  there is no float-to-mmx operation needed, because
720  only the float tag word info is corruptible)
721 */
722 #ifdef MMX_TRACE
723 
724 #define emms() \
725  { \
726  printf("emms()\n"); \
727  __asm__ __volatile__ ("emms");
728  }
729 
730 #else
731 
732 #define emms() __asm__ __volatile__ ("emms")
733 
734 #endif
735 
736 #endif
737 
mmx_ok
static int mmx_ok(void)
Definition: mmx.h:241
mm_support
static int mm_support(void)
Definition: mmx.h:70
zoom_filter_mmx
void zoom_filter_mmx(int prevX, int prevY, Pixel *expix1, Pixel *expix2, int *brutS, int *brutD, int buffratio, int precalCoef[16][16])
_PIXEL
Definition: goom_graphic.h:55
draw_line_mmx
void draw_line_mmx(Pixel *data, int x1, int y1, int x2, int y2, int col, int screenx, int screeny)
ATTR_ALIGN
#define ATTR_ALIGN(align)
Definition: attributes.h:64
mmx_t::uq
unsigned long long uq
Definition: mmx.h:55
attributes.h
zoom_filter_xmmx
void zoom_filter_xmmx(int prevX, int prevY, Pixel *expix1, Pixel *expix2, int *lbruS, int *lbruD, int buffratio, int precalCoef[16][16])
goom_graphic.h
BUFFPOINTNB
#define BUFFPOINTNB
Definition: filters.c:80
mmx_t
Definition: mmx.h:53
PERTEMASK
#define PERTEMASK
Definition: filters.c:86
DRAWMETHOD
#define DRAWMETHOD
Definition: drawmethods.c:22
mmx_t::q
long long q
Definition: mmx.h:54
emms
#define emms()
Definition: mmx.h:732
draw_line_xmmx
void draw_line_xmmx(Pixel *data, int x1, int y1, int x2, int y2, int col, int screenx, int screeny)
PERTEDEC
#define PERTEDEC
Definition: filters.c:88
xmmx_supported
int xmmx_supported(void)
config.h
mmx_supported
int mmx_supported(void)